When forming a metal interconnection in a semiconductor device, a first metal layer is typically formed on a semiconductor substrate or a dielectric. A buffer layer for inhibiting copper from diffusing can be deposited. An interlayer metal dielectric (IMD) layer is then typically formed on the buffer layer. Next, a via/trench process is performed, and a metal barrier layer is formed on the IMD layer. The via/trench is generally filled with copper to form a contact and a second metal layer. The metal barrier layer not in the via/trench is removed by performing a planarization process.
FIG. 1 is a cross-sectional view of a metal layer having a height difference thereon.
As described above, referring to FIG. 1, copper is generally deposited on a semiconductor substrate or a dielectric 10 to form a first metal layer 20. A buffer layer (not shown) and an IMD layer (not shown) are deposited on the first metal layer 20.
When the buffer layer and the IMD layer are deposited, a thermal stress is exerted on the first metal layer 20. The thermal stress acts to concentrate copper ions to a triple point of a copper crystalline structure.
Therefore, a hill-shaped height difference 22 is generated on the first metal layer 20.
The height difference 22 is then generated along surfaces of the buffer layer, the IMD layer, and the metal barrier layer formed on the first metal layer 20. Also, the area and the height of the height difference gradually increases on each subsequent layer.
Accordingly, the metal barrier layer is typically not uniformly planarized due to the height difference thereon.
In addition, the operation of chemical mechanical polishing (CMP) equipment is generally controlled by the polishing speed of each layer, and the CMP equipment stops when the IMD layer is reached during the metal barrier layer polishing process. With the IMD layer acting as an etch stop for the CMP process, a height difference in a portion of the IMD layer caused by the hill-shaped surface defect of the first metal layer may cause the CMP to stop polishing before all of the metal barrier layer is removed. This is because the CMP equipment determines that the entire surface of the metal barrier layer was planarized from a sensing of an exposed top surface of the IMD layer.
When a substantial portion of the metal barrier layer not in the via and/or trench remains, a contact and second metal layer disposed in the via/trench can be shorted. Therefore, operation reliability and product yield of the semiconductor device can be significantly degraded. Accordingly, there exists a need in the art for an improved method of manufacturing a semiconductor device.